Study QuoteOpen book
Master VHDL by focusing on clear logic; the simplest explanation often reveals the most efficient hardware design.
In hardware description languages, complexity is the enemy of stability. When we strip away jargon and focus on a plain explanation of data flow, the physical implementation becomes more predictable.
Try this: Take a complex VHDL module you have written and attempt to explain its function to a non-engineer in three sentences. If you cannot, refine the code for better readability.
Free Range VHDL
Bryan Mealy and Fabrizio Tappero